A newly developed fast and flexible CPU notification requires no polling

Getting interrupted while at work can cause you to lose your ability to work quickly and effectively. A computer’s central processing unit (CPU) core is no different. If the CPU core has to stop what it is working on each time a new task is assigned, the whole system can get bogged down and slow significantly.

Researchers in Purdue University’s Department of Computer Science have developed a new method that does not use polling, which is a system that devotes an entire CPU to checking and routing the traffic. The issue with this method is that it is often inefficient and the CPU could be better used for other tasks.

A smarter, faster notification system

The researchers presented their findings at the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). The publication was awarded the 2025 Best Paper Award at the 2025 ASPLOS Conference.

Wasted CPU cores are extremely important for data centers and cloud computing, and this discovery is expected to be adopted by CPU manufacturers to make data centers more efficient.

The research was led by Berk Aydogmus, a computer science Ph.D. student, and the principal investigator is his advisor, Kazem Taram, assistant professor of computer science in the College of Science.

“In computer systems, CPU cores are usually responsible for handling all kinds of events,” Taram explained. “For example, when we receive data from a network interface, the CPU will get interrupted and now has to switch from what it is doing to handle the received data.

“This has overhead on the CPU, as the CPU has to switch between tasks; just like when someone interrupts you when you are talking about important things and that causes overhead in your brain as it becomes harder/slower to come back to the important thought. On the other hand, we also want to process the incoming network data as fast as possible, but this interrupt method is slow as switching to handling network is slow.”

This discovery impacts cloud systems and large data centers, which would in turn impact the entire computational chain of users. It would drive efficiency at the top, which translates to smoother operations throughout the networks.

“CPUs in data center and cloud systems are required to handle all types of events quickly, as there are billions of events that they need to handle every second,” Taram said. “Examples of events that the CPU handles are receiving a packet from the network, scheduling a new task (preemption) on a processor core, and the completion of a task by other modules in the system like Graphics Processing Units (PGUs). Being efficient at handling these events can improve the performance and energy efficiency of data centers.”

Solving the polling problem

Taram explained that his work is more efficient than polling, which has an entire CPU core constantly checking for events, like incoming task flows.

“You can think of it as similar to when you constantly refresh your email when you expect an important email. This is obviously wasteful because you can’t do anything else while you are constantly refreshing,” he said.

“Similarly, polling wastes CPU cores that can be employed to do something useful or simply put to sleep for improving energy. This work presents an alternative to this wasteful method, called extended interrupt (xUI),” Taram said. “XUI reduces the interrupt overhead on the CPU, and we make the interrupts fast enough that we don’t need to rely on polling and waste CPU cores. They can keep doing the important jobs and we notify them by these fast interrupts, and they switch to handle events with minimal overhead.”

Taram works in the field of computer architecture and security. His research focuses on high-performance CPU architectures, microarchitectural attacks, high-performance mitigations, and architecture support for security and privacy. He is also a member of The Center for Education and Research in Information Assurance and Security (CERIAS).

“All the modern high-performance processors right now flush the in-flight instructions when they receive an interrupt,” Taram said. “The novelty of this work is that it shows that we don’t actually need to flush those instructions, leading to efficiency of dealing with interrupts.”

Other members of the research team are from the University of California San Diego. They are: Ph.D. student Linsong Guo, Ph.D. student Danial Zuberi, research scientist Tal Garfinkel, professor Dean Tullsen and assistant professor Amy Ousterhout.